Static random access memory (SRAM) devices have the characteristics of high speed and low power consumption. Therefore, SRAM devices are widely used in personal communications devices and consumer electronics.
FIG. 1 is a circuit diagram of a basic SRAM cell structure that may be used for embodiments of the present invention. Referring to FIG. 1, a basic SRAM cell includes two pull-up transistors (PU1 and PU2), two pull-down transistors (PU1 and PU2), and two pass-gate transistors (PG1 and PG2).
As feature sizes continue to decrease, fin-type transistors, such as fin field effect transistors (finFETs), have been used to replace planar transistors in logic devices. Some transistors (e.g., PU1) may be formed on a fin. For example, the gate of PU1 is formed on the fin, and the source region and the drain region of PU1 are formed on the regions on opposite sides of the gate. Thus, when a contact is formed on the source region of PU1 (i.e., the contact for applying a power supply voltage Vdd), the contact area is limited due to the small area of the fin, resulting in a large contact resistance.